đź“–The RISC-V Instruction Set Manual Volume I: Unprivileged ISA
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- authors
- RISC-V Unprivileged Horizontal Committee
- url
- https://drive.google.com/file/d/1uviu1nH-tScFfgrovvFCrj7Omv8tFtkp/view
- p.13 Hart is a parallel execution thread. It can be a CPU thread, or OS thread, or something else.
- p.13 Execution Environment Interface (EEI) is an environment where code is executed and defines what harts are available, memory, how privileged instruction and traps are handled, etc. It can be native/CPU environment (RISC-V supervisor binary interface/SBI?), an operating-system’s ABI, etc. It can be pure software, pure hardware, or a mix
- p.15 64-bit instruction set is not a superset of 32 bit instruction set. This means that 32-bit code can’t be ran unchanged on 64-bit CPUs. This is done because supersetting actually doesn’t help much. There are differences in traps/syscalls/software calling conventions/etc, so that implementing 32-bit instruction set in 64-bit CPU would still require mode switching. SPARC and MIPS initially designed 64-bit ISA as a superset of 32-bit ISA but they are now deprecating running 32-bit code on 64-bit ISA unchanged
- RISC-V is organized as one of base integer instruction sets (RV32I, RV64I, RV32E, RV64E) + extensions.
- p.17 memory is circular
- (guess this is easily implemented by just truncating/ignoring higher bits)
- (does it make it harder for compiler/analyzers?)
- p.19 all-zero and all-one instructions are illegal. this helps to trap when processors jumps to uninitialized memory
- p.23 RV32I has 40 instructions
- p.41 RV32E/RV64E are the same as RV32I/RV64I except that number of registers is reduced from 32 to 16. Instructions can only specify x0-x15 as registers. All encodings specifying other registers are reserved